CSES - Datatähti 2018 alku - Results
Submission details
Task:Bittijono
Sender:ollpu
Submission time:2017-10-10 21:54:55 +0300
Language:Assembly
Status:READY
Result:100
Feedback
groupverdictscore
#1ACCEPTED7
#2ACCEPTED15
#3ACCEPTED27
#4ACCEPTED51
Test results
testverdicttimegroup
#1ACCEPTED0.06 s1details
#2ACCEPTED0.06 s1details
#3ACCEPTED0.05 s1details
#4ACCEPTED0.04 s1details
#5ACCEPTED0.03 s1details
#6ACCEPTED0.05 s1details
#7ACCEPTED0.06 s1details
#8ACCEPTED0.04 s1details
#9ACCEPTED0.04 s1details
#10ACCEPTED0.04 s1details
#11ACCEPTED0.06 s2details
#12ACCEPTED0.05 s2details
#13ACCEPTED0.05 s2details
#14ACCEPTED0.04 s2details
#15ACCEPTED0.05 s2details
#16ACCEPTED0.05 s2details
#17ACCEPTED0.07 s2details
#18ACCEPTED0.05 s2details
#19ACCEPTED0.05 s2details
#20ACCEPTED0.06 s2details
#21ACCEPTED0.06 s3details
#22ACCEPTED0.05 s3details
#23ACCEPTED0.06 s3details
#24ACCEPTED0.04 s3details
#25ACCEPTED0.05 s3details
#26ACCEPTED0.04 s3details
#27ACCEPTED0.05 s3details
#28ACCEPTED0.05 s3details
#29ACCEPTED0.05 s3details
#30ACCEPTED0.05 s3details
#31ACCEPTED0.05 s4details
#32ACCEPTED0.08 s4details
#33ACCEPTED0.06 s4details
#34ACCEPTED0.09 s4details
#35ACCEPTED0.08 s4details
#36ACCEPTED0.07 s4details
#37ACCEPTED0.12 s4details
#38ACCEPTED0.09 s4details
#39ACCEPTED0.09 s4details
#40ACCEPTED0.11 s4details

Code

; assembly korvaa rubyn, eikö?
section .bss
input resb 10
output resb 50
A resb 2000000
B resb 2000000
section .text
global _start
_start:
; Read and parse input
mov rax, 0
mov rdi, 0
mov rsi, input
mov rdx, 10
syscall
call parse
; rdi = rax/2+rax%2
mov rdi, rax
shr rdi, 1
mov rsi, 1
and rsi, rax
add rdi, rsi
call solve
mov rax, 1
mov rdi, 1
; rsi and rdx retained from solve
; Swap rdx <-> rsi
xor rdx, rsi
xor rsi, rdx
xor rdx, rsi
syscall
; Exit
mov rax, 60
mov rdi, 0
syscall
parse:
mov rax, 0
mov rdi, input
mov rsi, 0
.loop:
mov sil, [rdi]
sub rsi, '0'
cmp rsi, 0
jl .done
cmp rsi, 9
jg .done
mov rdx, 10
imul rax, rdx
add rax, rsi
inc rdi
jmp .loop
.done:
ret
solve:
; rax = n, rdi = n/2+n%2
; Fill A and B
mov rsi, 0
.fill_loop:
mov rbx, A
mov [rbx + rsi*4], eax
mov rbx, B
mov [rbx + rsi*4], esi
inc rsi
; if rsi < rdi: continue
cmp rsi, rdi
jl .fill_loop
; Iterate until some m bit string ends
.iterate:
mov rsi, 0
.it_loop:
mov rbx, A
mov ecx, [rbx + rsi*4]
mov rbx, B
mov edx, [rbx + rsi*4]
mov rbp, rcx
shr rbp, 1
cmp rdx, rbp
jg .it_greater
.it_less:
sub rcx, rdx
dec rcx
jmp .it_over
.it_greater:
mov rbx, rdx
mov rdx, rcx
sub rdx, rbx
mov rcx, rbx
dec rcx
.it_over:
cmp rcx, 0
jne .skip
cmp rdx, 0
je .iterate_over
.skip:
mov rbx, A
mov [rbx + rsi*4], ecx
mov rbx, B
mov [rbx + rsi*4], edx
inc rsi
cmp rsi, rdi
jl .it_loop
jmp .iterate
.iterate_over:
; rsi contains optimal m
mov rbx, rsi
mov rsi, 0 ; string index
mov rcx, 0 ; current bit
.result_loop:
mov rbp, rax
shr rbp, 1
cmp rbx, rbp
jg .rs_greater
.rs_less:
sub rax, rbx
dec rax
jmp .rs_over
.rs_greater:
mov rdx, rbx
mov rbx, rax
sub rbx, rdx
mov rax, rdx
dec rax
xor rcx, 1
.rs_over:
add rcx, '0'
mov rdx, output
mov [rdx + rsi], cl
sub rcx, '0'
inc rsi
cmp rax, 0
jg .result_loop
mov rdx, output
mov [rdx + rsi], byte `\n`
inc rsi
ret

Test details

Test 1

Group: 1

Verdict: ACCEPTED

input
1

correct output
1

user output
0

Test 2

Group: 1

Verdict: ACCEPTED

input
2

correct output
11

user output
00

Test 3

Group: 1

Verdict: ACCEPTED

input
3

correct output
10

user output
01

Test 4

Group: 1

Verdict: ACCEPTED

input
4

correct output
1111

user output
0000

Test 5

Group: 1

Verdict: ACCEPTED

input
5

correct output
110

user output
001

Test 6

Group: 1

Verdict: ACCEPTED

input
6

correct output
101

user output
010

Test 7

Group: 1

Verdict: ACCEPTED

input
7

correct output
1110

user output
0001

Test 8

Group: 1

Verdict: ACCEPTED

input
8

correct output
1100

user output
0011

Test 9

Group: 1

Verdict: ACCEPTED

input
9

correct output
1101

user output
0010

Test 10

Group: 1

Verdict: ACCEPTED

input
10

correct output
1001

user output
0110

Test 11

Group: 2

Verdict: ACCEPTED

input
38

correct output
1101011

user output
0010100

Test 12

Group: 2

Verdict: ACCEPTED

input
13

correct output
11011

user output
00100

Test 13

Group: 2

Verdict: ACCEPTED

input
90

correct output
111001010

user output
000110101

Test 14

Group: 2

Verdict: ACCEPTED

input
25

correct output
110010

user output
001101

Test 15

Group: 2

Verdict: ACCEPTED

input
82

correct output
111001101

user output
000110010

Test 16

Group: 2

Verdict: ACCEPTED

input
94

correct output
1100011110

user output
0011100001

Test 17

Group: 2

Verdict: ACCEPTED

input
100

correct output
1111001001

user output
0000110110

Test 18

Group: 2

Verdict: ACCEPTED

input
99

correct output
110010010

user output
001101101

Test 19

Group: 2

Verdict: ACCEPTED

input
98

correct output
110110010

user output
001001101

Test 20

Group: 2

Verdict: ACCEPTED

input
92

correct output
100110001

user output
011001110

Test 21

Group: 3

Verdict: ACCEPTED

input
1666

correct output
101101100100101

user output
010010011011010

Test 22

Group: 3

Verdict: ACCEPTED

input
897

correct output
11101001101010

user output
00010110010101

Test 23

Group: 3

Verdict: ACCEPTED

input
4466

correct output
111101010110100101

user output
000010101001011010

Test 24

Group: 3

Verdict: ACCEPTED

input
4240

correct output
11011001011010101

user output
00100110100101010

Test 25

Group: 3

Verdict: ACCEPTED

input
3089

correct output
1011001010100101

user output
0100110101011010

Test 26

Group: 3

Verdict: ACCEPTED

input
4697

correct output
11010101101010110

user output
00101010010101001

Test 27

Group: 3

Verdict: ACCEPTED

input
4608

correct output
11010110101001010

user output
00101001010110101

Test 28

Group: 3

Verdict: ACCEPTED

input
4625

correct output
111011001100101001

user output
000100110011010110

Test 29

Group: 3

Verdict: ACCEPTED

input
4611

correct output
11010101010101100

user output
00101010101010011

Test 30

Group: 3

Verdict: ACCEPTED

input
4917

correct output
10110100101010110

user output
01001011010101001

Test 31

Group: 4

Verdict: ACCEPTED

input
178555

correct output
1011010110110101010110110

user output
0100101001001010101001001

Test 32

Group: 4

Verdict: ACCEPTED

input
864856

correct output
10111010110110100100101010010

user output
01000101001001011011010101101

Test 33

Group: 4

Verdict: ACCEPTED

input
112146

correct output
1101110101011001100100110

user output
0010001010100110011011001

Test 34

Group: 4

Verdict: ACCEPTED

input
741124

correct output
1011010011010101100101011010

user output
0100101100101010011010100101

Test 35

Group: 4

Verdict: ACCEPTED

input
511902

correct output
1011010100011010100101001110

user output
0100101011100101011010110001

Test 36

Group: 4

Verdict: ACCEPTED

input
920019

correct output
11100100101101010101001101010

user output
00011011010010101010110010101

Test 37

Group: 4

Verdict: ACCEPTED

input
933943

correct output
10101011010100100110100111001

user output
01010100101011011001011000110

Test 38

Group: 4

Verdict: ACCEPTED

input
973410

correct output
1011010101011010101010101001

user output
0100101010100101010101010110

Test 39

Group: 4

Verdict: ACCEPTED

input
954943

correct output
10110110010011010100100110101

user output
01001001101100101011011001010

Test 40

Group: 4

Verdict: ACCEPTED

input
911674

correct output
1010110010110101010101010110

user output
0101001101001010101010101001